The present invention is directed to a calculation unit, which may be configured as a multiplier or a divider for binary numbers.
Hardware adders are frequently encountered in digital circuitry. They can be fabricated using a reasonable number of gates. Hardware subtractors can also be found, frequently based on adders employing compliment arithmetic. However, since hardware circuitry for binary multiplication would require an excessive number of gates, the multiplication function is usually implemented by multiple additions or by the shift-and-add method. Because both of these techniques are relatively slow, a hardware multiplier would be desirable in order to execute multiplications rapidly.
Multiplication tables are nearly as old as civilization itself. Indeed, archeologists have found multiplication tables inscribed on clay tablets while excavating ancient ruins in the Middle East. In more modern times, multiplication tables from 0.times.0 through 9.times.9, along with an algorithm for using these tables to multiply numbers of virtually any size, are taught to gradeschool students.
It would seem to be a relatively straightforward task to make a hardware multiplier by using a look-up memory which stores a multiplication table. For example, half of the address pins of a ROM could receive a first binary number A, and the remaining half of the address pins could receive a second binary number B, with each storage location in the ROM storing the product of a particular value for A times a particular value for B. There is, however, a serious flaw in this approach--the number of memory locations required would expand rapidly as the number of bits in the numbers A and B increases. In other words, the number of bits in A and B must be relatively small if a ROM having a practical number of addressable locations is to be used.